The goal of this article is to show how to create a simulation script in VHDL to make a binary multiplier hardware in sequential form, multiplying 10 by 19, giving 190. in output.

In a run_file.tcl file, we type the following script commands:

This file allows us to launch the simulation with the desired signals directly, see chronogram at the end of the report.

In a multiplication.vhd file, we define a mult entity with ports of type std_logic_vector of 8 input bits and 16 output bits. The rest of the signals are of type std_logic.

In a single rtl architecture, the different blocks of the data path are defined using following concurrent assignment instructions and supplemented with a description of the sequencer using of 2 processes.

In a testmult.vhd file, we define a test architecture to validate our architecture.

For the following inputs :

• multiplier = 10
• multiplicand = 19

We have the following: output = 190.

The wave is this one:

Our timetable is very consistent.

We therefore created a simulation script in VHDL to make a binary multiplier hardware in sequential form, multiplying 10 by 19, giving 190.

This article is part of my Electronics posts blog, in which you can find few articles about things i learnt in my post-graduated school :)